Time interval averaging circuit

ABSTRACT

A circuit to measure the average time interval that occurs between recurring electrical signals. Independent input channels control the passage of periodic clock pulses through a gate such that only complete clock pulses are passed through the gate. The number of clock pulses that occur during 10N time intervals (where N is an integer) is totalized and displayed.

mite States Patent [72] Inventor Rolf Schrnldhauser [56] ReferencesCited [21] A 1 N 2: UNITED STATES PATENTS pp o. Filed g 27, 19702,877,413 3/1959 Muehlner 324/186 [45] Patented Dec. 28, 1971 PrimaryExaminer-Alfred E. Smith [73] Assignee Hewlett-Packard CompanyAttorney-A. C. Smith Palo Alto, Calit.

ABSTRACT: A circuit to measure the average time interval [54] TIMEINTERVAL AVERAGING CIRCUIT that occurs between recurring electricalsignals. Independent 3Clalms,2Drawing Figs. input channels control thepassage of periodic clock pulses through a gate such that only completeclock pulses are passed 2? through the gate. The number of clock pulsesthat occur durn Go 11/06, ing time intervals (where N is an imeger) is(named and 501 Field of Search 324/186,

Q A L BU Q J JE 23 I 19 1! STA 1 J INPUT? 5 0 D Q I I ll r- R C I L I TjCLOCK GATING MEANS COUNTING CLOCK MEANS F A "T AND DISPLAY MEANS C I 27I i i\ I 1' r 1 53, 123.456 1 1 I as J 13" 3 I F 39 55 STOP (IL I, 1 I lN INPUT pL Q D 0 [L 1] +10 31 l R C 6 L 51 l 1 -33 I L .8

STOP CONTROL MEANS AVERAGING MEANS 63 PATENTEIJ nacze I97! 3153134 TARTCONTROL MEANS 23 19 l! sum 13 M d- Q 0 Q H -R c TE; Y CLOCK GATING MEANS29 couunuc CLOCK MEANS F "T I c A|\ I27 I msmv mus 123.456 25 L 65 I 4143 3?' 39 I (55 STOPC 1 I u INPUT p 5 Q 0 Q P-ss A I R -c 6 7 R33 L STOPCONTROL mus 45 Figure 1 CLOCK PULSES II F1 Fl J H F] a START SIGNALS l bSTOP SIGNALS M l l TRUE LEVEL OUTPUT 13 F'" "'1' 3T l""7 l d TOW 105 TO?OUTPUT 33 I T l e x FALSE LEVEL 7 OUTPUT 35 L T OUTPUT 2T n lure 2mvENToR ROLF 'SQHMIDHAUSER TIME INTERVAL AVERAGING CIRCUIT BACKGROUND OFTHE INVENTION Certain known techniques for measuring the time intervalbetween two signals include a source of periodic clock pulses which isconnected to a gate. commonly called a clock gate. A first signal isused to enable the clock gate and thereby pass clock pulses of knownfrequency through the gate. A second signal is used to disable the clockgate and thereby inhibit the passage of clock pulses through the gate.The clock gate output is typically connected to the input of apulse-shaping circuit which provides at its output a single pulse forevery complete input pulse. The output of the pulse-shaping circuit iscounted and the time interval between the first and second signals isproportional to the number of pulses counted. The shortest time intervalthat can be resolved with this measurement technique is determined bythe period of clock pulses from the source of periodic clock pulses.

Typically. the opening and closing of the clock gate is unsynchronizedwith the periodic clock pulses and thereby an error of plus or minus oneclock period is introduced into the measurement. This error can begreatly reduced and the resolution of the measurement greatly improvedsuch that time intervals shorter than a clock period can be measured bytaking the average of a number of time interval measurement.

One disadvantage of known time interval measurement techniques is thatthe clock gate may be enabled and/or disabled during a periodic clockpulse and the output of the clock gate may be a fraction of a completeclock pulse. The number of pulses produced by pulse-shaping circuits inresponse to a fraction of a clock pulse cannot be statisticallydetermined and may be zero, one or even two pulses. As the number oftime intervals averaged is increased. the number of pulses produced bythe pulse-shaping circuits in response to fractions of clock pulsesbecomes a significant source of error in the measurement.

SUMMARY OF THE INVENTION The present invention provides a circuit tomeasure the average time interval that occurs between recurringelectrical signals. The number of clock pulses that are passed through aclock gate during time intervals are totalized and displayed. The numberN is an integer which may be selected by a switch. The display includesa decimal point that is positioned in response to the number N selected.

The opening and closing of the clock gate of the present invention issynchronized with periodic clock pulses such that only complete clockpulses are passed through the clock gate and thereby significant errorsthat are caused by the clock gate passing fractions of a clock pulse areeliminated.

DESCRIPTION OF THE DRAWING FIG. 1 is a drawing of the preferredembodiment of the invention.

FIG. 2ag are graphs showing typical waveforms produced by the apparatusin FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. I there isshown the time interval averaging circuit. Start control means 23 has astart input 11 connected to the set input of set/reset flip-flop 19.Output 0 of flip-flop I9 is connected to the D" input ofa conventionalD- type flip-flop 21. A clock means 25 is connected to clock input 17 ofstart control means 23 to provide clock pulses as shown in FIG. 2a tothe clock input of flip-flop 21. A signal appearing at start input 11,as represented in FIG. 2b, causes flipflop 19 to set. Flip-flop 19 beingset prior to the leading edge of a clock pulse appearing at the clockinput of flip-flop 21 causes output 0 of fiip-flop 21 to switch to atrue level upon the trailing edge of the clock pulse. Output 0 offlip-flop 21 forms output 13 of start control means 23 and FIGS. 20, 2band 2d show this output switching upon the trailing edge of a clockpulse applied at input 17 of start control means 23 to a true level inresponse to a signal applied at input I] of start control means 23.

Stop control means 45 has a stop input 31 connected to the set side ofset/reset flip-flop 37. Output 0 of flip-flop 37 is connected to the D"input of conventional D-type flip-flop 39. Clock means 25 is connectedto clock input 43 of stop control means 45 to provide clock pulses asshown in FIG. 2a to the clock input of flip-flop 39. A signal appearingat stop input 31, as represented in FIG. 2c, causes flip-flop 37 to set.Flip-flop 37 being set prior to the leading edge of a clock p ulseappearing at the clock input of flip-flop 37 causes output 0 offlip-flop 39 to attain a false level and output Q of flip-flop 39 toattain a true level upon the trailing edge of the clock pulse as shownin FIGS. 211, 2c, 22 and 2}". Output 6 of flip-flop 39 forms output 33of stop control means 45 and output 0 of flipflop 39 forms output 35 ofstop control means 45.

For any time interval whose start signal sets flip-flop 19 prior to theleading edge of a clock pulse appearing at clock input 17 and whose stopsignal sets flip-flop 37 after the lead ing edge of the same clock pulseappears at clock input 43, outputs 13 and 33 of start means 23 and stopmeans 45 respectively will be at similar true levels 101 simultaneouswith the trailing edge of that clock pulse, as shown in FIGS. 20' and22. These outputs will remain in this condition until a stop signal setsflip-flop 37 prior to the leading edge of a clock pulse appearing atclock input 43. The example in FIG. 2 shows such a stop signal occurringshortly after the leading edge of a clock signal. Upon the trailing edge103 of the next clock signal output 33 switches to a false level andoutput 35 switches to a true level as shown in FIGS. 2e and 2f.

For any time interval whose start and stop signals set flipflops l9 and37 respectively prior to the leading edge of a clock signal appearing attheir clock inputs, outputs 13 and 33 will be at dissimilar levels 107as shown in FIGS. 2d and 22.

Output 35 is connected to reset inputs l5 and 41 of start and stopcontrol means 23 and 45 respectively, and is used to reset the start andstop control means upon the trailing edge of the clock pulse that occursafter output 33 is switched to a false level as shown in FIGS. 2d, 2eand 2f.

Clock gating means 29 has a clock input C connected to the clock means25. Inputs A and B are connected to outputs I3 and 33 of start and stopcontrol means 23 and 45 respectively. Clock gating means 29 is enabledby a true level output from start control means 23. Start control means23 assures that the true level output never occurs during a clock pulse.The initial state of output 33 of stop control means 45 is a true levelas shown in FIG. 22, and therefore clock pulses appearing at clock inputC are allowed to pass through the clock gating means when a true leveloutput appears at input A of the clock gating means. Clock gating means29 is disabled in response to a false level at input B from output 33 ofstop control means 45. The stop control means 45 assures that the falselevel output will occur only after a number of complete clock pulses haspassed through the clock gating means, as represented in FIG. 2g.

Output 35 of stop control means 45 is connected to input 51 of averagingmeans 63. Input 51 is connected to the input of a conventional decadedivider assembly 55 which is responsive to the number of time intervalsthat have occurred and provides an output to binary flip-flop 57. OutputQ of flip-flop 57 is connected to AND-gate 59 of averaging means 63 forenabling gate 59 during 10 time intervals, where N is an in teger thatcan be manually selected by conventional techniques. Output 27 of clockgating means 29 is connected to input 53 of averaging means 63 which isconnected to an input of AND-gate 59. The output of this gate formsoutput 61 of averaging means 63 which is connected to display meansDisplay means 65 is a conventional decade counting assembly thattotalizes and displays the number of clock pulses passed by gate 59during 10"" time intervals. The display means includes a decimal pointindicator that is initially positioned in response to the number Nselected. An increase in N by one causes the decimal point to be shiftedone place to the left. A decrease in N by one causes the decimal pointto be shifted one place to the right. In this way the requisiteaveraging is accomplished.

It should be noted that to make an average time interval measurement therepetition rate of the recurring start and stop signals must not be anexact multiple of a subharmonic of the clock rate from the clock means25. This requirement assures that the recurring start and stop signalswill not occur at the same point in time between clock pulses andtherefore a highly accurate statistical average can be obtained.

Therefore, the present invention includes a circuit to measure theaverage time interval that occurs between recurring electrical signals.Only complete clock pulses are passed through the clock gate andtherefore the measurement is independent of errors which would otherwisebe introduced with conventional time interval measurement techniques.

What is claimed is:

1. Apparatus for measuring the average time interval that occurs betweenrecurring start and stop signals the apparatus comprising:

control means having start and stop inputs and having an output normallyat a false level for producing a true level output in response to astart signal being applied at said start input and for returning to saidfalse level output in response to a stop signal being applied at saidstop input;

a source of periodic clock pulses;

clock gating means having a first input connected to said source ofperiodic clock pulses and a second input connected to said control meansoutput and having an output responsive to a true level at said secondinput for passing clock pulses through said clock gating means duringsuch time as the true level signal is maintained at said second input;

averaging means having an output and having an input A connected to thestop input of said control means and an input B connected to the outputof said clock gating means for counting the number of stop signals thatappear at input A and for passing through to said output such clockpulses that appear at input B between the first and the 10 stop signal,where N is in integer;

means for selecting the number N of time intervals to be averaged; and

means to count and display the output of said averaging means, saidmeans including a decade counting assembly having a decimal pointindicator responsive to the means for selecting the number N.

2. Apparatus as in claim 1 wherein said averaging means comprises:

main gating means having an input B connected to receive clock pulsesfrom said clock gating means and an input C to control the time intervalduring which clock pulses will be allowed to pass through said maingating means and having an output; and

counting means having an input A connected to receive signals thatrepresent the occurrence of a time interval and having an outputconnected to said input C of said main gating means to enable said maingating means in response to a first time interval having occurred and todisable said main gating means in response to l0 time intervals havingoccurred.

3. Apparatus as in claim 1 wherein:

said control means has a clock input connected to said source ofperiodic clock pulses for producing said true level output simultaneouswith the trailing edge of a clock pulse appearing at said clock input inresponse to a signal appearing at said start input prior to theappearance of a clock pulse at said clock input and in the absence of asignal appearing at said stop input prior to the appearance of saidclock pulse and for producing said false level output simultaneous withthe trailing edge of a clock pulse that a pears at said clock inputafter a si nalhas appeare at said stop input for gating throug saidclock gating means only complete clock pulsesv

1. Apparatus for measuring the average time interval that occurs between recurring start and stop signals, the apparatus comprising: control means having start and stop inputs and having an output normally at a false level for producing a true level output in response to a start signal being applied at said start input and for returning to said false level output in response to a stop signal being applied at said stop input; a source of periodic clock pulses; clock gating means having a first input connected to said source of periodic clock pulses and a second input connected to said control means output and having an output responsive to a true level at said second input for passing clock pulses through said clock gating means during such time as the true level signal is maintained at said second input; averaging means having an output and having an input A connected to the stop input of said control means and an input B connected to the output of said clock gating means for counting the number of stop signals that appear at input A and for passing through to said output such clock pulses that appear at input B between the first and the 10N stop signal, where N is an integer; means for selecting the number N of time intervals to be averaged; and means to count and display the output of said averaging means, said means including a decade counting assembly having a decimal point indicator responsive to the means for selecting the number N.
 2. Apparatus as in claim 1 wherein said averaging means comprises: main gating means having an input B connected to receive clock pulses from said clock gating means and an input C to control the time interval during which clock pulses will be allowed to pass through Said main gating means and having an output; and counting means having an input A connected to receive signals that represent the occurrence of a time interval and having an output connected to said input C of said main gating means to enable said main gating means in response to a first time interval having occurred and to disable said main gating means in response to 10N time intervals having occurred.
 3. Apparatus as in claim 1 wherein: said control means has a clock input connected to said source of periodic clock pulses for producing said true level output simultaneous with the trailing edge of a clock pulse appearing at said clock input in response to a signal appearing at said start input prior to the appearance of a clock pulse at said clock input and in the absence of a signal appearing at said stop input prior to the appearance of said clock pulse and for producing said false level output simultaneous with the trailing edge of a clock pulse that appears at said clock input after a signal has appeared at said stop input for gating through said clock gating means only complete clock pulses. 